System Configuration
The SpiNNaker2 STM interface provides utilities for configuring voltage and frequency settings on the board.
Voltage Configuration
Setting Bus Voltage
from spinnaker2_stm.configure import set_bus_voltage
# Set voltage for 0.5V power lane
set_bus_voltage(domain=0, voltage=0.5)
# Set voltage for 0.8V power lane
set_bus_voltage(domain=1, voltage=0.8)
The set_bus_voltage function accepts:
domain: Power lane selection (0 for 0.5V, 1 for 0.8V)voltage: Target voltage value- For 0.5V domain: must be between 0.3V and 0.8V
- For 0.8V domain: valid range depends on hardware
show_output: Whether to print operation feedback (default: True)ser_path: Serial interface path (default: "/dev/ttyACM0")
Frequency Configuration
Setting PE and NoC Frequencies
from spinnaker2_stm.configure import set_pl_and_frequency
# Configure PE and NoC frequencies
set_pl_and_frequency(
pe_pl=1, # PE power lane
pe_freq=125, # PE frequency in MHz
noc_pl=1, # NoC power lane
noc_freq=125 # NoC frequency in MHz
)
The system will:
- Load or create a frequency lookup table
- Generate the necessary configuration code
- Update the relevant system files with new timing parameters
Frequency Code Generation
For lower-level frequency configuration, use freq_code_gen:
from spinnaker2_stm.configure import freq_code_gen
freq_cfg = [
125, # PE frequency (MHz)
125, # NoC frequency (MHz)
1, # PE division lane
1, # NoC division lane
0x1234, # PLL config 0
0x5678, # PLL config 1
1, # div0
1, # div1
1, # div2
1 # div3
]
freq_code_gen(freq_cfg, has_timer=True)
This will:
- Update PLL configuration registers
- Set PE and NoC clock dividers
- Configure power lane settings
- Update timer frequencies if required
Reference Clock
The system uses a reference clock of 100 MHz (JIB1_CLK_REF). This is used as the base for all frequency calculations.
Error Handling
The configuration functions include basic error checking:
- Invalid voltage ranges
- Invalid power domain selections
- File access errors during configuration updates
For example: